the entire work.
This series of books on computer architecture is the fruit of over 30 years of travels in the electronic, microelectronic and computer worlds. I hope that it will provide you with sufficient knowledge, both practical and theoretical, to then specialize in one of these fields. I wish you a pleasant stroll through these different worlds.
IMPORTANT NOTES.– As this book presents an introduction to the field of microprocessors, references to components from all periods are cited, as well as references to computers from generations before this component appeared.
Original company names have been used, although some have merged. This will allow readers to find specification sheets and original documentation for the mentioned integrated circuits on the Internet and to study them in relation to this work.
The concepts presented are based on the concepts studied in selected earlier works (Darche 2000, 2002, 2003, 2004, 2012), which I recommend reading beforehand.
Philippe DARCHE
August 2020
Introduction
This volume details how to program a microprocessor in five chapters. The first two chapters demonstrate the three characteristics of ISA (Instruction Set Architecture, cf. § V1-3.5), which are: instruction encoding, addressing modes and the instruction set of a generic component. Then, additional notions linked to the instruction set and execution are discussed in the third chapter. This primarily involves the notion of illegal, invalid, reserved and trusted instructions, the notion of memory alignment, orthogonality and the symmetry of the instruction set, as well as the notion of pure, re-entrant and relocatable code. Then, the subjects of execution time, memory requirements, execution modes, portability and virtualization will be discussed. Finally, it ends with aspects that are very important in industry, their hardware and software compatibilities, how to measure execution performances and the criteria for choosing a microprocessor or MPU (MicroProcessor Unit). The last two chapters study two ways of altering execution flow. These are the concepts of the sub-program and interruption.
NOTE.– The choice has been made to write the names of registers in upper case in the text and figures but in lower case in assembly language, since the norm (IEEE 1985) does not specify which case to use. The name of the instructions is in lower case in the text and programs (MIPS (Microprocessor without Interlocked Pipeline Stages) style), sometimes also in upper case (Motorola or Arm® style). Moreover, the examples given refer to current and older microprocessors and computer processors for the purposes of instruction. This chapter is not intended to be exhaustive. It mainly presents the functions of the first MPUs. It will be completed by the following two books. The instructions cited will be complemented by MPU documentation or in a specialist work.
1
Coding and Addressing Modes
This chapter focuses on two important characteristics of Instruction Set Architecture (ISA) (cf. § V1-3.5), which are instruction encoding and addressing modes.
1.1. Encoding and formatting an instruction
The instruction1 is represented in a computer using a binary word in the format i bits, a multiple of the format n of the data and, in general, a multiple of the byte. We use the expression machine code to mean all those binary words representing the instruction to be executed. Instruction encoding depends on the architecture of the target processor. It is formed at least of an instruction code and, potentially, of one or more operands as Figure 1.1 illustrates.
Figure 1.1. Breakdown of an instruction
This instruction can be broken down into fields2. The instruction code, also called operation code (abridged to opcode), in format c, has one or more fields. The essential one is the function code. It defines the operation to be executed. Its format of f bits defines the maximum number of instructions F (= 2f) in the instruction set3. Other fields can be added to this such as, for example, one that specifies the addressing mode (the addressing mode field) of the operands to the format as Figure 1.2 illustrates (VAX4 approach from the Digital Equipment Corporation (DEC)). The processor therefore has 2a addressing modes. Besides simplifying the encoding, one benefit is to separate the encoding of the function from that of the address, which makes it possible to make the instruction set symmetrical (cf. § 3.1.3). This instruction code generally takes the format of the data n of the processor to optimize access to primary memory. Since in our example n is fixed, the architect of the microprocessor or MPU (MicroProcessor Unit) must therefore compromise between the number of instructions and the number of addressing modes if the field exists. One field may be favored to the detriment of the other.
Figure 1.2. An example of the structure of an operation code
If the instruction requires, the operation code is followed by one or more operand fields (Figure 1.3), and their number is dependent on the operation (unary or binary) and the architecture. This operand field in the format o bits makes it possible to specify, depending on the addressing mode chosen, the value of the reference of the location of the operand needed for calculation or, potentially, the result. An operand's storage location, which is imposed by the programmer, compiler or linker or architecture, is a register or memory location. An instruction to one operand is called a “monadic”, and one with two operands, “dyadic”. When there are two operands, we speak of source and destination operands or sink operands or sometimes simply left and right operands. We cite the VAX mini-computer with a variable format as an example of encoding. The operation code included one to two bytes. It was eventually followed by no more than six operand specifiers, mainly address specifiers, making it possible to design the operand. The MPU MC6800 instruction format included one to three bytes, the first being an operation code indicating the addressing mode.
Figure 1.3. Format of an instruction with two operands
Table 1.1 shows the different address combinations for IA-32 instruction set (IA for Intel Architecture, also called i386). Combinations not indicated are not possible either due to the architecture or to their incoherence. We cite impossible memory (to) memory combinations in most architectures, as it is necessary to pass through a register and an immediate-register or immediate-memory, which cannot be done because of the impossibility of allocating a value to a constant.
Table 1.1. Possible address combinations in family IA-32
| Operands | |
| Destination | Source |
| Register | Immediate |
| Memory | Immediate |
| Register | Register |
| Memory |
Register
|