Since this signal depends upon the DUT, correcting for it is more complicated.
3 RF signal that leaks from the test set switch, to port 2, and reflects off the DUT output match into the port 2 transmission test mixer. As this signal depends upon the DUT characteristics, correcting for it can also be more complicated. Modern VNAs that use separate sources instead of test set switches eliminate this source of crosstalk.
4 The final source of signal leakage is related to any test fixture or probing done to connect to the DUT. Leakage from port 1 to port 2 of the probes or fixtures is usually electric field radiation or magnetic field coupling between the ports. Since these fields are non‐TEM, they do not remain constant with changes in the DUT characteristics, and their effect may not be well understood. Probe‐to‐probe isolation is a key problem in measurements, but one that is not well accounted for. Careful fixture or probe design that includes shielding is perhaps the best solution to this final leakage effect.
In most modern VNAs, the design of the mixers and LO isolation networks are such that the level of the first three sources of crosstalk are at or below the noise floor of the receiver. As such they can be ignored except in special cases where extended dynamic range is desired, as discussed in Chapter 6. The fourth cause of crosstalk is inherent in the fixtures or probes, and it can sometimes be removed with calibration. But since the source is often due to radiation from one port to the other, this radiation pattern depends in a complex way on the actual loading of the port and the structure of the DUT. For example, in a probed situation, leaving the probes up as an “open” calibration standard can cause the probes to act as E‐field antennas and can produce crosstalk between the probes. Grounding the probes, to produce a short, can cause magnetic field coupling between the probes, again producing crosstalk. Both of these crosstalk terms are non‐TEM, meaning they have E and H fields that propagate in the direction from port 1 to port 2. Normal calibration methodologies do not correct for non‐TEM crosstalk as their values do not remain constant if the DUT configuration changes.
2.2.6 IF and Data Processing
The final hardware portion of the VNA block diagram is the IF processing chain. The VNA receiver converts the RF signal to a first IF frequency, which is further converted and detected in the IF processing path. In older analyzers, such as the HP‐8510, this consisted of a synchronous analog second‐converter that produced two DC outputs proportional the real and imaginary portions of the RF voltage at the receiver input. These DC voltages were measured with DC analog‐to‐digital converters (ADCs) that produced a digital representation of the real and imaginary values. More modern IF structures such as in the HP‐8753 or HP‐8720 used a second stage of IF down‐conversion to bring the IF signal down to a frequency where an AC ADC could directly sample the waveform. The final IF frequency was set by the sampling rate of the ADC.
2.2.6.1 ADC Design
Now, most modern VNAs incorporate a high‐speed ADC and perform direct sampling of the first IF signal. An example of a VNA digital‐IF block diagram is shown in Figure 2.23. The IF signal is preconditioned with adjustable gain to optimize the signal‐to‐noise ratio in the ADC. For some applications, it is useful to have a narrowband pre‐filter before the ADC so that the IF can be switched between a wideband IF and a narrowband response. An anti‐alias filter is used just before the ADC, with a bandwidth of about one‐third to one‐fourth that of the ADC clock rate.
Figure 2.23 Digital IF block diagram.
The FPGA that processes the ADC readings can be configured as a digital second converter of flexible IF frequency, so the final digital IF frequency can be quite arbitrary. There are several modes of operation for the digital IF. For these high‐speed ADCs, the raw ADC readings have very high bit rates. Some of the latest designs for VNAs have four channels of data, at 16 bits and 100 mega‐samples per second to produce a data rate of 6.4 Gbps. Specialized conditioning of the signal and advanced digital signal processing (much of which is proprietary) can improve the performance of the IF ADCs to many more effective bits.
At these high data rates, the main CPU cannot process the data fast enough to keep up, so an FPGA is used to decimate and filter the signals before the processed data is sent to the main processor using shared DMA memory. The function of decimation and filtering is the basic data processing step of any digital IF; in this function, a measurement is performed by setting the source and receiver frequencies so that the first IF contains the signal of interest. The ADC samples the IF signal, typically with two to four times over sampling, although it can be as much as 60 or 100 times over sampled. A finite set of samples is processed by the FPGA to produce a final result that represents the real and imaginary parts of the signal being measured. For example, if the digital IF is operating at 100 Msps, the IF frequency is 10 MHz, and the IF filter is set to 100 kHz IF BW, then approximately 10 μs of data are captured, or approximately 1000 data samples. These 1000 samples are processed by a multiply‐add chain in the FPGA to both filter the response and extract the real and imaginary values. In this way, the 1000 samples are reduced to two samples.
A second mode of operation for the digital IF is “ADC capture” mode. In this mode, the FPGA does not process the data; rather, the data samples are simply captured into the local memory in the digital IF for a finite period of time. The entire ADC data stream is available for any further processing that might be beyond the algorithms available in the FPGA. Some modern VNAs have memory depths up to 4 Gb allowing deep memory captures. This mode of operation, while not typical, is useful for capturing anomalous effects such as transient or pulsed responses, as well as more complicated functions such as de‐modulation of IF signals.
2.2.7 Multiport VNAs
For a class of RF and microwave devices, the normal port count of two to four ports is not sufficient, and multiport measurements are required. There are two distinct classes of multiport test requirements that generate the need for two distinct RF architectures to support the measurements. In the past, RF switching test sets provide the basis for these multiport extensions, but recently true‐multiport VNAs have been introduced.
The first class of devices requires multiple sets of 2‐, 3‐, and 4‐port measurements. As such, the native mode measurements of the VNA are sufficient, and all that is required is RF switching to route the VNA ports to the various port pairs of the DUT. One example of such a DUT is a satellite multichannel‐diplexer (or multiplexer), which filters and separates signals from a common antenna path to each of several output channels, as shown in Figure 2.24. This unit has waveguide filters and interconnections to provide for the lowest possible loss.
Figure 2.24 A satellite multiplexer with many outputs.
Source: Courtesy ComDev Ltd., with permission.
This device requires two‐port measurements for each path from the common port so a 2‐port VNA with one common port and one switch port can make all the required measurements. These are sometimes known as switching test sets or simple switch trees.
The second class of devices requires a measurement from each port to every other port, and in general the response of any path depends upon the loading or match applied to every other port. A “Butler matrix” is a kind of signal dividing network used in phased‐array radar systems, which has this attribute.