Digital System Design using FSMs. Peter D. Minns

clock is used as a qualifier in states s1 and s3 so that the output P is only logic 1 in these two states. However, state s3 has an additional qualifier x, so in s3 P = 1 only when in s3 and then only if input signal x is true in s3.

      Then in state s3, the output P will only obtain a clock pulse if the x input happens to be logic 1.

      You can see that if x = 0 then, when the input s is raised to logic 1, the FSM will produce the sequence 100 at output P. Therefore, P = s1 + s3·x. If x = 1 then, when s is raised to logic 1, the FSM will produce a 101 sequence at the output P.

      This FSM is an example of a Mealy FSM since the output P is a function of both the state and the inputs clock and x, i.e. both clock and x are fed forward to the output decoding logic.

       The reader could easily modify the FSM so that the 100 sequence at P was produced if x = 1, and the 101 sequence produced if x = 0. Therefore, now:

       Produce the Boolean equation for P in state s3 that would satisfy this requirement.

       Then assign a unit distance code to the state diagram; see Frames 1.12and 1.13.

       Finally, when you have done that, try producing a timing diagram of the modified FSM.

When you’ve finished, turn to Frame 1.20.

Frame 1.20

       Produce the Boolean equation for P in state s3 that would satisfy this requirement.

      The Boolean equation for P which will produce a 101 sequence when x = 0 is:

      P = s3·/x.

Note you do not need to indicate the clk, as it is assumed. Also note that in this case qualifying with NOT x (/x), rather than with x, as in Figure 1.22.

Figure 1.22 State diagram with Mealy P output in s3.

      It is very likely that you came up with a different set of values for the secondary state assignments to those obtained. This is fine since there is no real preferred set of assignments, apart from trying to obtain a unit distance coding (ABC values not shown at this stage).

       Try re‐drawing the state diagram with the dummy state and modified coding.

      Note: care should be taken where you place the dummy state. If you added a dummy state between states s1 and s2, for example, it would alter the P output sequence so that, instead of producing, say, 101, the sequence 1001 would be produced.

      A safe place to add a dummy state would be between states s3 and s4, or between states s4 and s0 since they are outside the ‘critical P’ sequence generating in this part of the state diagram.

Turn to Frame 1.21 for the timing waveform diagram solution.

Frame 1.21 The Timing Waveform Diagram Solution

      The solution is, of course, based on the secondary state assignments used, so your solution could well be different if you have used a different SSV pattern.

In this solution (Figure 1.23), the author has deliberately arranged for the x input to change to logic 0 inside of the clock pulse equal to 1 in state s3 just to illustrate the effect that this would have on the output P. You can see that the output pulse on P is not a full clock high period.

Figure 1.23 Timing diagram showing the effect of input x on output P.

       This is a very realistic event since the outside world input x (and, indeed, any outside world input) can occur at any time.

Turn to Frame 1.22.

Frame 1.22

      At this point in the course we have covered the basics of what an FSM is and how a state diagram can be developed for a particular FSM design.

      The reader has also seen how the outputs of the FSM depend upon the SSVs (these are covered in Chapter 3).

      The SSVs can be arbitrarily assigned, but that following a unit distance code is good practice.

      The reader has looked at a number of simple designs and seen how a Mealy or Moore FSM can be realized in the way in which the output equations are formed.

      We have not yet seen how the state diagram can be realized as a circuit made up of logic gates and flip‐flops, but this part of the development process is very much a mechanized activity which is covered in detail in Chapter 3.

      The next section looks at a number of FSM designs in an attempt to give you some feel for the design of state diagrams for FSMs. The pace will be a little quicker as I will assume that you have understood the previous work.

      You may like to take a well‐earned break at this point!

      For more details, see Minns (1995).