R.Figure 4.14 State diagram of high‐low alarm FSM.Figure 4.15a The event‐driven high‐low FSM with sampling input sp.Figure 4.15b Logisim circuit for the high‐low alarm FSM.Figure 4.16 How to keep to unit distance coding.Figure 4.17 An event cell using NAND sequential equation.Figure 4.18 Motor problem with fault detection and test input.Figure 4.19 Motor with fault detection.Figure 4.20 Logisim circuit of motor with fault detection and test input.Figure 4.21 Verilog HDL simulation of motor with fault detection and test in...Figure 4.22 A typical electromechanical relay.Figure 4.23 State diagram for relay event equations.Figure 4.24 Circuit diagram for the relays showing all components.Figure 4.25 Logic circuit for the same arrangement.Figure 4.26 The motor with fault and test input.Figure 4.27 The Verilog HDL simulations.Figure 4.28 Block diagram and state diagrams of the mower FSM.Figure 4.29 Circuit for the mower FSM.Figure 4.30 The Verilog HDL simulation for the two‐state FSM.
5 Chapter 5Figure 5.1 First one hot state diagram with design equations.Figure 5.2 Basic circuit for a one hot clocked design.Figure 5.3 Clocked one hot example.Figure 5.4 The state diagram.Figure 5.5 Using Logisim with tunnels.Figure 5.6 An example for you to complete,Figure 5.7 The state diagram again to compare against your equations.Figure 5.8 Another example showing effect of two‐way branch.Figure 5.9 Same example with s3 invariant state.Figure 5.10 Compare state diagram with equations.Figure 5.11 Seven‐state FSM example.Figure 5.12 FSM data acquisition system.Figure 5.13 State diagram for the data acquisition system.Figure 5.14 Simulation for the data acquisition system.Figure 5.15 Seven‐state one hot FSM.Figure 5.16 Memory tester FSM.Figure 5.17 State diagram of memory tester with outputs.Figure 5.18 The octal data latch and comparators.Figure 5.19 Adding the FSM to the block diagram.Figure 5.20 The state diagram of the FSM.Figure 5.21 A Verilog HDL simulation of the FSM system.
6 Chapter 6Figure 6.1 Test bench of logic gates FSM.Figure 6.2 Example using s and p inputs.Figure 6.3 Logisim circuit for the s and p input FSM.Figure 6.4 Using one input in each transition.Figure 6.5 Sequential equations for Figure 6.4.Figure 6.6 The circuit of the system.Figure 6.7 Motor problem with fault.Figure 6.8 Motor with fault and test input.Figure 6.9 Logisim circuit details.Figure 6.10 Simulation showing its details.Figure 6.11 State diagram for event‐driven one hot example note equations.Figure 6.12 Two‐state one hot event circuit using Logisim.Figure 6.13 Block diagram for three‐handshake FSM.Figure 6.14 The three‐handshake state diagram.Figure 6.15 The three‐handshake circuit.
7 Chapter 7Figure 7.1 One hot state diagram alongside Petri net.Figure 7.2 Petri net with two placeholders.Figure 7.3 The one hot state machine and two placeholder Petri nets.Figure 7.4 The join mechanism.Figure 7.5 Both Pn and Pm must have a token before a join can be completed....Figure 7.6 The result of a join.Figure 7.7 The result of a fork.Figure 7.8 The effect of conflict and overflow.Source: Fernandes, J. M. et a...Figure 7.9 How to overcome conflict and overflow.Figure 7.10 Handling two‐way branches.Figure 7.11 A two‐placeholder Petri net.Figure 7.12 The same Petri net to compare the equation.Figure 7.13 Pump motor example using sequential Petri net.Figure 7.14 Circuit for the pump motor Petri net.Figure 7.15 Work out equations from the Petri net.Figure 7.16 Completed equations for the Petri net.Figure 7.17 The Petri net, equations, and circuit.Figure 7.18 The Logisim circuit diagram.Figure 7.19 A clock‐driven Petri net.Figure 7.20 An event‐driven Petri net.Figure 7.21 Forks and joins in a Petri net.Figure 7.22 The forking mechanism.Figure 7.23 Example of parallel to sequence.Figure 7.24 Used to compare the equations.Figure 7.25 A running example of the action of the Petri net.Figure 7.26 Starting from placeholder P1.Figure 7.27 Now waiting for transition from P2 via T2.Figure 7.28 Waiting for the inputs P and Q.Figure 7.29 After input P.Figure 7.30 After input Q.Figure 7.31 After input syn2.Figure 7.32 Two separate Petri nets.Figure 7.33 An enabling arc affecting transient T5.Figure 7.34 A disabling arc to transient T5.Figure 7.35 The effect of both enabling and disabling arcs.Figure 7.36 How a Petri net can be used to share a printer between two compu...Figure 7.37 The Petri net solution for the shared resource.Figure 7.38 The Verilog HDL simulation for the shared resource.Figure 7.39 Sample shot of a Windows program to design Petri nets.Source: Pe...Figure 7.40 The shared printer between two computers.Figure 7.41 The shared printer solution.Figure 7.42 The simulation output.Figure 7.43 The protocol structure for the Petri net controller.Figure 7.44 Block diagram for the Petri net serial clock driven controller....Figure 7.45 The Petri net FSM – note the use of enabling arcs to synchronize...Figure 7.46 Simulation of the system.Figure 7.47 The use of a C gate to control signals.Figure 7.48 Workflow Petri Net Designer (WoPeD).
8 Appendix A1Figure A1.1 Basic gates using UK and USA symbols.Figure A1.2 Symbols for UK and USA gates and their characteristics.Figure A1.3 For OR gates using Boolean algebra.Figure A1.4 For AND gates using Boolean algebra.Figure A1.5 The effect of associate and commutative laws.Figure A1.6 Distributive laws and their use.Figure A1.7 Auxiliary rule in action.Figure A1.8 The effect of signal delay in AND/OR gates.Figure A1.9 The use of De‐Morgan’s rules.
9 Appendix A2Figure A2.1 Single pulse with memory block diagram.Figure A2.2 State diagram to help generating the equations.Figure A2.3 Circuit diagram of the final system.Listing A2.1 The Verilog HDL code.Figure A2.4 The addition of the test bench to the FSM.Figure A2.5 Screenshot of new project wizard using SynaptiCAD. Source: SYNAP...Figure A2.6 Screenshot of project window to show some of the options availab...Figure A2.7 The yellow compile and green simulate buttons in SynaptiCAD.Figure A2.8 Simulation of the FSM in SynaptiCAD.Figure A2.9 Screenshot of Logisim window with menu and part of circuit.Sourc...Figure A2.10 The operation of a D type flip‐flop.Figure A2.11 What a logic gate will look like on the screen.Figure A2.12 The gate menu and some of the items that can be changed.Source:Figure A2.13 Part of the beginner’s tutorial.Figure A2.14a The state diagram with design equations.Figure A2.14b Complete circuit of the FSM drawn in Logisim.Figure A2.15 What a Logisim screen might look like using the truth table app...Figure A2.16 Example screenshot of counter with use of oscilloscope.Figure A2.17 The same FSM as Figure A2.14b but using Tunnels.Figure A2.18 This version uses Logisim‐Evolution – note different flip‐flops...Figure A2.19 Sample of a shift register using Tunnels.
10 Appendix A3Figure A3.1 A four‐bit Karnaugh map and its states.Figure A3.2 Four‐bit up counter of how each T type is based around a D type ...Listing A3.1 Four‐bit synchronous counter (TFF).Figure A3.3 Simulation of Listing A3.1.Figure A3.4 A single flip‐flop of the parallel loading counter (bit slice)....Figure A3.5 Single bit slice of parallel loading shift register using D type...Figure A3.6 Counter sequence using D type flip‐flops.Figure A3.7 Typical circuit of a gate crystal oscillator with overtone suppr...Figure A3.8 Details for the design of twisted ring counter using don’t care ...Figure A3.9 Typical four‐bit parallel loading shift register.Figure A3.10 Simulation of a parallel loading shift register.Figure A3.11 How to deal with input st and output ACK using an FSM.Figure A3.12 How the timing T1 to T4 relates to the Ck, CE, IOW, and st sign...Figure A3.13 Shows T1 to T4 and the ACK input signal.Figure A3.14 The FSM‐based data acquisition system with sample and hold inpu...Figure A3.15 State diagram for the data acquisition system.Figure A3.16 Circuit for the Logisim simulation of the FSM.
11 Appendix A4Figure A4.1 State diagram for single/multiple‐pulse generator with memory FS...Listing A4.1 Single‐pulse multi‐pulse generator.Listing A4.2 The test bench module.Figure A4.2 Verilog HDL simulation of its operation as Listing A4.2.Listing A4.3 Memory tester ‐ behavioural mode.Figure A4.3 Verilog HDL simulation of Listing A4.3.
12 Appendix A5Figure A5.1 Diagram of the system for the programmable FSM.Figure A5.2 The parallel loading up counter and its inputs and outputs.Figure A5.3 The operation of an eight‐input multiplexer.Figure A5.4 The operation of an eight‐bit memory device.Figure A5.5 The instruction set for the programmable FSM.Figure A5.6 Shows how the IBF instruction can be implemented.Figure