these improvements are studied in detail by several researchers. Some of these are discussed in the present chapter.
In section 1.2, various theoretical explorations by different scientists are included. Since the early 1950s, various researchers have studied the impact of strain on material and device properties and these observations are reported in various reputed journals. It has been found that by inducing strain, band structure of a material can be altered and as a result, the behavior of the materials changes too. Therefore, fundamental process of stress and strain calculations through theoretical analysis becomes very important. In this section, basic steps of strain matrix formation, two different types of strain, biaxial and uniaxial, formalism are discussed. These are the main stress components researchers have used for the last couple of decades in transistor to further explore their impact on device performance. In this regard, the impact of induced strain on device performance parameters is also explored by several scientists, and these calculations are also briefly included.
In section 1.3, different studies are discussed where impact of induced strain on device performance is calculated by using different standard simulation software. In the last few decades various simulation software have been designed to reduce the fabrication cost and time while exploring new ideas. These software are well accepted by all communities and used in an efficient manner to predict the possible impact under different scenarios. The present author has also performed several studies on strain engineering in MOSFET and FinFET devices by using Synopsis TCAD process and device simulators and the results are briefly discussed in this section. In addition, published simulation results by various other authors are also included.
In the following section 1.4, various experimental data published by scientists in reputed journals and conferences are discussed in brief. These results give an idea on the experimentally achievable data in this field of strain engineering. These experimental observations also indicate that the theoretical and simulated predictions are well calculated and by using this strain engineering technique, performance of modern nano-scale transistors can be improved significantly.
Future Scope
The present chapter presents how strain technology has developed over the years. Starting from theoretical analysis, through various simulation and fabrication processes, the scientists have studied the physics of strain engineering and how it can be used in modern transistors to improve the performance. Although gradual miniaturization of transistor dimension was performed for several years to accommodate more transistors in a chip, with the challenges of low-dimensional transistor devices, scientists are looking for new device structures, materials, and technologies to sustain the growth. In this regard, various III-V semiconductor materials like InGaAs, GaAs, InP, etc., as well as several new two-dimensional materials like Graphene, Molybdenum Sulfide (MoS2), Boron Nitride, etc., are under investigation for their superior characteristics compared to conventional group-IV semiconductors. In these materials, researchers are exploring the impact of induced stress by controlled manner; however, several studies need to be performed to reach a definite conclusion. Furthermore, in new device structures like Nanowire (NW) FETs, Quantum well (QW) FETs, 2D channel material FETs, etc., these strain-induced changes in device performances, need to be explored in detail. Plenty of studies need to be undertaken for future devices and with the help of previously published reports, these new analyses will lead to innovative new technologies and ideas.
Acknowledgement
The author wants to mention special thanks to Prof. Hafizur Rahaman, Indian Institute Engineering Science and Technology (IIEST) - Shibpur, and Dr. Sanatan Chattopadhyay, University of Calcutta, India, for providing me several valuable suggestions and comments during the entire work.
References
1. J.E. Lilienfeld, US Patent 1, 745, 175, (1930, filled October 26, 1926), 1, 877, 840 (1932, filled December 8, 1928), and 1, 900, 018 (1933, filled March 28, 1928).
2. Moore G. E. (1965) Cramming more components onto integrated circuits. Electronics. 38. 114-117.
3. Sverdlov Viktor (2011) Strained Induced Effect in Advanced MOSFETs. Springer Wien. New York. US.
4. Sun Y., Thompson S. E., & Nishida T. (2010) Strain Effect in Semiconductors. Springer. New York. US.
5. Hall H.H., Bardeen J., & Pearson G.L. (1951) The effects of pressure and temperature on the resistance of p-n junctions in germanium. Phys. Rev. 84(1). 129–132.
6. Smith CS. (1954) Piezoresistance effect in germanium and silicon. Phys Rev. 94. 42–49.
7. Herring C., & Vogt E. (1956) Transport and deformation-potential theory for many-valley semiconductors with anisotropic scattering. Phys Rev. 101. 944–961.
8. Manasevit HM, Gergis IS, & Jones AB. (1982) Electron mobility enhancement in epitaxial multilayer Si-Si1−xGex alloy films on (100) Si. Appl Phys Lett, 41. 464–466.
9. People R., Bean J.C., Lang D.V., Sergent A.M., Stormer H.L., Wecht, V, Lynch R.T., & Baldwin K. (1984) Modulation doping in GexSi1-x / Si strained layer heterostructures. Appl Phys Lett. 45. 1231.
10. Maity C. K, Bera L K, & Chattopadhyay S (1998) Topical Review: Strain Si heterostructure field effect Transistor. Semiconductor Science Technology. 13. 1225-1246.
11. Dalapati Goutam Kumar, Chattopadhyay Sanatan, Kwa Kelvin S. K., Olsen Sarah H., Tsang Y. L., Agaiby Rimoon, O’Neill Anthony G., Dobrosz Piotr, & Bull Steve J. (2006) Impact of strained-Si thickness and Ge out diffusion on gate oxide quality for strained-Si surface channel n-MOSFETs. IEEE Transaction on Electron Devices. 53(5). 1142–1152.
12. Ghani T., Armstrong M., Auth C., Bost M., Charvat P., Glass G., Hoffmann T., Johnson K., Kenyon C., Klaus J., McIntyre B., Mistry K., Murthy A., Sandford J., Silberstein M., Sivakumar S., Smith P., Zawadzki K., Thompson S., & Bohr M. (2003) A 90nm high volume manufacturing logic technology featuring novel 45nm gate length strained silicon CMOS transistors. IEEE Int. Electron Devices Meeting Tech. Digest. p.11.6.1.
13. Thompson S.E., Sun G., Wu K., Lim J., & Nishida, T. (2004) Key differences for process-induced uniaxial vs. substrate-induced biaxial stressed Si and Ge channel MOSFETs. IEEE Int. Electron Devices Meeting Tech. Digest. 221–224.
14. Lim J.S., Thompson S.E., & Fossum J.G. (2004) Comparison of threshold-voltage shifts for uniaxial and biaxial tensile-stressed n-MOSFETs. IEEE Electron Device Letters. 25. 731–733.
15. Numata T., Mizuno T., Tezuka T., Koga J., & Takagi, S. (2005). Control of threshold-voltage and short-channel effects in ultrathin strained-SOI CMOS devices. IEEE Trans. Electron Devices. 52(8). 1780–1786.
16. Takagi S., Hoyt J.L., Welser J.J., & Gibbons J.F. (1996) Comparative study of phonon limited mobility of 2 dimensional electrons in strained and unstrained Si MOSFET’s. J. Appl. Phys. 80. 1567.
17. Zhang W., & Fossum J.G. (2005) On the threshold voltage of strained-Si-Si1-xGex MOSFETs. IEEE Trans. Electron Devices. 52. 263–268.
18. Martin J. S., Bournel A., Monsef F., Chassat C., & Dollfus P. (2006) Multi sub-band Monte Carlo simulation of ultrathin double gate MOSFET with 2-D electron gas. Semicond. Sci. Technol. 21. 29–31.
19. Michielis M. D., Esseni D., Tsang Y. L., Palestri P., Selmi L., O’Neill A. G., & Chattopadhyay S. (2007) A Semianalytical Description of the Hole Band Structure in Inversion Layers for the Physically Based Modeling of pMOS Transistors. IEEE Trans. Electron Devices. 54. 2164-73.
20. Batwani H., Gaur M., & Jagadesh Kumar M. (2009) Analytical drain current model for nanoscale strained-Si/SiGe MOSFETs. COMPEL - International Journal for Computation and Mathematics in Electrical and Electronic Engineering. 28(2).