and drain region Si, GaAs semiconductor materials.
Table 2.2 summarizes the extracted design parameters for DG - TFET, shown in Figure 2.1(a) and Figure 2.1(b). As shown in Table 2.2, all the design parameters of DG - TFET such as ION, IOFF, ION/IOFF and SS have improved significantly as per requirements while ambipolar current (Iamb) is reduced drastically.
2.5 Results and Discussion
The drain current (IDS) in the DG -TFET, which is estimated by B2B tunneling and governed by popularly known as Kane’s model [18, 19]. The tunneling probability of charge carried in tunnel-based devices is estimated by the known WKB model written as Equation 2.1 [25–27]. These popular models show strong dependency of tunneling transport phenomena on device geometry, materials and induced electric field inside the device. Both popular Equations (2.1 & 2.2) provide sufficient facilities in term of process and technology to optimize device characteristics and performance by choice of appropriate device geometry and materials.
Table 2.2 Lists of computed electrical parameters of double gate (a) hetero structure (b) homo structure tunneling FET.
| Design parameter | High - k dielectric (HfO2 ≈ 25) | |
| Homo - DG -TFET | Hetero - DG -TFET | |
| ION (A/µm) | 4.0 × 10-6 | 4.0 × 10-6 |
| IOFF (A/µm) | 1.0 × 10-18 | 1.0 × 10-20 |
| ION/IOFF | 4.0 × 1012 | 4.0 × 1014 |
| SS (mV/dec) | 39. 68 | 34.25 |
| Iamb (A/µm) | 5.0 × 10-11 | 1.0 × 10-19 |
The most common technique suggested by a device expert is gate dielectric engineering. In this technique, instead of SiO2 (k ≈ 3.9), other popular gate dielectric materials, for example, Si3N4 (k ≈ 12), ZrO2 (k ≈ 24) and HfO2 (k ≈ 25) are commonly used. The used high - k dielectric materials, instead of SiO2, increases the internal electric field, improves the electrostatic performance of TFETs [19, 26]. Figure 2.4 and Figure 2.5 show the impact of high - k gate dielectic on DG -TFET. Both Figures (2.4 & 2.5) indicate an even higher on-current (ION) and decreased subthreshold swing (SS) with higher high - k dielectric materials. Table 2.3 and Table 2.4, have the extracted device design parameters of DG - TFET. During investigation and from Table 2.3 and Table 2.4, it has been observed that the various design parameters such as ION, IOFF, ION/IOFF, SS, Iamb for both homo and hetero DG -TFET have been improved. But hetero DG -TFET shows superiority than homo DG -TFET due to improved electric field with reduced effective tunneling bandgap. As shown in Figure 2.2 and Figure 2.3, this is possible due to improved electric field inside the device and reduced effective bandgap inside the tunneling region at the interface of Si/GaAs. This effective reduced bandgap in case of hetero DG -TFET, reduces the tunneling window as shown in Figure 2.3.
Figure 2.4 Transfer characteristic of homo structure double gate TFET.
Figure 2.5 Transfer characteristic of hetero structure double gate TFET.
Table 2.3 Lists of computed design parameters of the homo structure DG -TFET with various gate dielectric materials.
| Design parameters | Gate dielectric material (Homo structure Si/Si/Si) | |||
| HfO2 (k ≈ 25) | ZrO2 (k ≈ 24) | Si3N4 (k ≈ 12) | SiO2 (k ≈ 3.9) | |
| Vth(V) | 0.55 | 0.55 | 0.80 | 0.85 |
| SS(mV/decade) | 39.68 | 39.71 | 42.73 | 45.00 |
| ION(A/μm) | 4.0 × 10-6 | 3.90 × 10-6 | 5.00 × 10-7 | 1.00 × 10-7 |
| IOFF(A/μm) | 1.00 × 10-18 | 1.00 × 10-18 | 1.00 × 10-18 | 1.00 × 10-18 |
| ION/IOFF | 4.00 × 1012 | 3.90 × 1013 | 5.0 × 1011 | 1.00 × 1011 |
Table 2.4 Lists of computed design parameters of the hetero structure DG -TFET with various gate dielectric materials.
| Design parameters |
| |||